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ASIC Physical design FCL Lead
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Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/…

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Physical Design Engineer

Softnautics
Ahmedabad, Gujarat

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Job details

Qualifications

Node.js
Electronics Engineering
Master's degree
Bachelor's degree
Perl
Scripting
Communication skills

Full job description

Job Description

We are seeking a Senior Physical Design Engineer with 6 years of experience to lead the physical implementation of our advanced semiconductor projects. You will play a crucial role in shaping the silicon realization of our cutting-edge designs, ensuring their successful integration from RTL to tape- out.

Responsibilities

Provide technical guidance, mentoring to physical design engrs.
Interface with front-end ASIC teams to resolve issues.
Low Power Design – Voltage Islands, Power Gating, Substrate-bias techniques.
Timing closure on DDR2/DDR3/PCIE interfaces.
Excellent communication skills.
Strong Background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
Expertise in scripting languages such as PERL, TCL.
Strong Physical Verification skill set.
Static Timing Analysis in Primetime or Primetime-SI.
Good written and oral communication skills. Ability to clearly document plans.
Ability to interface with different teams and prioritize work based on project needs.

Skill Set

Required Skills

He/she should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
He/she should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification.
Bachelor’s or Master’s degree in electronics engineering or related field

Desired Skills

Familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, Mentor Calibre
Knowledge of low power design techniques and implementation

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Physical Design Engineer

ASIC Physical design FCL Lead

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Lead Physical Design Engineer

Physical Verification Engineer

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