Date posted 06/07/2026
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Physical Design Engineer, Staff Level
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years turning RTL into silicon that actually works, not just passes checks, but works at speed, at power, under real-world conditions. You know that the difference between a design that tapes out clean and one that comes back with surprises is usually a floorplan decision made in week two or a timing constraint someone glossed over in the handoff. You catch those things before they become problems.
You are comfortable living in the space between synthesis and signoff, moving between Fusion Compiler, PrimeTime, and RedHawk without losing sight of what you are actually building. When a design does not close, you do not just run another iteration. You dig into the constraint, the cell placement, the IR drop map, and figure out what is actually wrong. You make calls without perfect information because waiting is not an option when tape-out is six weeks out.
You can talk to an IP architect about design intent and walk out with a floorplan that respects both performance and reality. You have been through enough tape-outs to know what good looks like, and you have strong opinions about methodology, constraints, and signoff quality. At Synopsys, you will work on interface IPs and subsystems that ship in products customers depend on, and the team will expect you to bring that judgment every day.
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Own the complete physical implementation flow from RTL to GDSII for high-performance interface IPs, test chips, and subsystems at advanced nodes
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Drive synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing using Synopsys tools including Design Compiler, ICC2, and Fusion Compiler
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Perform static timing analysis, EM/IR signoff, and physical verification to ensure designs meet all timing, power, and reliability targets
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Develop and refine implementation flows and CAD methodologies that improve turnaround time, PPA, and design predictability
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Interface directly with IP architects, verification teams, and product engineering to understand design constraints, deliverable formats, and customer requirements
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Debug complex timing, power, and physical issues across multi-million gate designs and make timely decisions under tape-out pressure
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Contribute to scripting and automation efforts using Perl, Tcl, and Python to streamline flows and improve design productivity
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Your implementation work will directly enable tape-outs of interface IPs and subsystems that ship in customer products across automotive, mobile, and data center markets
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The flows and methodologies you build will be reused across multiple projects, improving design quality and reducing time to tapeout for the entire team
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Your signoff rigor will reduce the risk of respins and ensure designs meet performance and reliability targets in silicon
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The constraints and timing models you develop will become the foundation for downstream integration and customer adoption
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Your ability to make sound technical decisions under pressure will keep projects on schedule and unblock teams when issues arise
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The automation and scripting you contribute will scale across the design team, freeing engineers to focus on harder problems
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Your collaboration with product and architecture teams will shape how designs are scoped, planned, and delivered to customers
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B.Tech or M.Tech in Electronics, Electronics & Communication, VLSI Design, Microelectronics, or equivalent
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5+ years of hands-on experience in ASIC physical implementation from RTL to GDSII at advanced process nodes
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Deep working knowledge of Synopsys tools including Design Compiler, ICC2, Fusion Compiler, PrimeTime, Star-RCXT, ICV, and RedHawk
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Proven track record of contributing to recent project tape-outs with responsibility for timing closure, signoff, or physical verification
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Strong scripting skills in Perl, Tcl, and Python for flow automation and CAD methodology development
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Solid understanding of timing constraint development, clock tree synthesis, EM/IR analysis, and physical verification flows
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Experience with IP subsystem implementation or multi-die integration is a strong plus
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You can look at a floorplan and know within minutes whether it will close on timing or create downstream problems
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When a design does not converge, you do not just rerun the tool, you open the timing report, trace the critical path, and figure out what constraint or structure is actually broken
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You make decisions independently and quickly because you have seen enough designs to know what matters and what does not
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You can explain a complex tradeoff between area, timing, and power to a product manager or architect in two sentences without losing the technical nuance
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You stay calm under tape-out pressure and help the team stay focused when schedules compress and issues pile up
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You push back when a constraint is unclear, a deliverable format does not make sense, or a methodology will create problems three months from now
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