Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.

You will serve was the organizational leader for regional security programs consisting of access control, loss prevention, workplace violence, intelligence…

As a Systems Media Architect within the Media Architecture Group at Micron, you will be responsible for the development and integration of cutting-edge media…

Perform functional verification, root cause design discrepancies, debug pre-silicon full chip designs and help resolve them.

Responsible for testing of high speed memory modules (DIMM) w.r.t functionality and performance that are produced in high volumes. Bachelor’s Degree or higher.

Build OPC and Sub-resolution Assist Feature (SRAF) recipes and implement at full chip scale. Build Inverse Lithography Technique (ILT) recipe for full die…

Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Experience in UVM Test Bench.

In depth knowledge and extensive experience with embedded firmware development. Expertise in the use of scripting languages, programming tools and environments.

Perform functional verification, root cause design discrepancies, debug pre-silicon full chip designs and help resolve them.

Build OPC and Sub-resolution Assist Feature (SRAF) recipes and implement at full chip scale. Build Inverse Lithography Technique (ILT) recipe for full die…

Provide leadership in building and growing a Custom layout team from the ground up to support Micron’s global DRAM layout requirement;

Build OPC model to validate and to predict wafer patterning for both R&D pilot chip and production parts. Build recipes of OPC and Sub-resolution Assist Feature…

You will partner cross-functionally and cross-site with R&D, Quality, Manufacturing, and other engineering groups to collaborate in developing strategies to…

Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.

Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.

Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.

You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally correct design.

Understanding of Big Data Engineering/processing, Business Intelligence and Advanced analytics. Knowledge on ETL/ELT Design and processes.

8-14 years of relevant experience in Synthesis/STA. Good understanding of overall design Flow RTL to GDS. Hands on Experience on Constraints Generation, timing…

Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Experience in UVM Test Bench.