Role Summary
The engineer will be responsible for verifying PCI Express (PCIe) and Compute Express Link (CXL) IPs or SoCs using SystemVerilog and UVM, ensuring protocol compliance, functional correctness, and verification closure.
Experience Required
- 5+ years in ASIC/SoC Design Verification/Design Verification
- Strong experience in PCIe and/or CXL protocol verification
- Excellent hands-on expertise in SystemVerilog (SV) and UVM (mandatory)
Key Responsibilities
- Develop and maintain UVM-based verification environments.
- Verify PCIe/CXL controller, endpoint, root complex, or subsystem designs.
- Write SystemVerilog testbenches, sequences, monitors, scoreboards, and assertions.
- Create constrained-random test scenarios.
- Debug RTL and verification failures.
- Drive functional coverage, code coverage, and regression closure.
- Perform protocol compliance verification.
- Work closely with RTL, architecture, and validation teams.
Mandatory Skills
- PCIe (Gen3/Gen4/Gen5/Gen6)
- CXL (Compute Express Link)
- SystemVerilog
- UVM
- ASIC Design Verification
- Functional Verification
- Constrained Random Verification
- Assertions (SVA)
- Coverage Closure
- Regression
- Debugging
Preferred Skills
- Cadence Xcelium
- Synopsys VCS
- QuestaSim
- VIP (Verification IP)
- AXI/AHB/APB
- Python/Perl/Shell scripting
- Git
- Jenkins
Pay: Up to ₹3,575,500.90 per year
Experience:
- SystemVerilog (SV) and UVM : 5 years (Required)
Work Location: In person
