We are looking for motivated interns who want to build practical skills in RTL design and digital verification. This internship is suitable for students or freshers who have basic knowledge of digital electronics and want to learn real semiconductor design and verification workflows.
The selected intern will work under guidance and get an opportunity to improve their understanding of RTL coding, simulation, debugging, verification concepts, and technical documentation.
Responsibilities:
- Learn RTL design concepts using Verilog/SystemVerilog.
- Understand digital blocks such as FSMs, counters, registers, FIFOs, memories, and interfaces.
- Read, update, and maintain RTL design and verification-related code.
- Write and improve simple testbenches for digital modules.
- Run simulations and debug compilation or functional issues.
- Analyze waveforms and verify expected design behavior.
- Help improve design examples, verification examples, and related technical material.
- Document observations, issues, fixes, and learning notes clearly.
- Coordinate regularly with the mentor/manager for assigned tasks.
Required Skills:
- Basic knowledge of digital electronics.
- Basic understanding of Verilog or SystemVerilog.
- Understanding of combinational and sequential circuits.
- Ability to read and understand simple RTL code.
- Basic problem-solving and debugging mindset.
- Willingness to learn design and verification concepts.
Good to Have:
- Basic exposure to testbenches and simulation tools.
- Knowledge of FSM, FIFO, counters, registers, and memories.
- Awareness of SystemVerilog verification concepts.
- Basic Linux command-line knowledge.
- Interest in VLSI, semiconductor design, or digital verification.
Eligibility:
- B.E./B.Tech/M.Tech students or freshers from Electronics, Electrical, VLSI, Embedded Systems, or related branches.
- Final-year students or recent graduates can apply.
- Candidates with a strong learning attitude and interest in semiconductor/VLSI domain are encouraged to apply.
What You Will Learn:
- Practical RTL design basics.
- Verilog/SystemVerilog coding style.
- Simulation and waveform debugging.
- Basic verification methodology.
- Testbench development and debugging.
- Industry-style design and verification workflow.
Pay: ₹8,000.00 - ₹15,000.00 per month
Work Location: In person
