Design Verification Engineer salaries in Telangana
₹11,89,343
avg per year
The average salary for Design Verification Engineer jobs near Telangana is ₹11,89,343.*
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Top Design Verification Engineer jobs near Telangana
View AllSenior PCB Design Engineer
Unistring Tech Solutions Pvt. Ltd.
Hyderabad, Telangana
24 months service for below 3 years’ experience candidates. Own complete schematic design (hierarchical design approach). Develop and validate circuit designs.
₹4,00,000 - ₹10,00,000 a year
Design Engineer
Purenergy limited
Sangareddy District, Telangana
1 to 3 years of relevant experience in mechanical/product design. We are looking for a skilled and motivated Design Engineer with 1–3 years of experience in…
₹20,000 - ₹30,000 a month
6 days ago
Design Verification Engineer with PCIE & IP Verification
ElevarSoC Technologies
Hyderabad, Telangana
Hiring Now: Design Verification Engineer. We are actively looking for a highly skilled Design Verification Engineer. Pay: ₹443,990.70 - ₹1,966,133.69 per year.
₹4,43,990.70 - ₹19,66,133.69 a year
Design verification engineer
Team Computers
Hyderabad, Telangana
Have exposure to PCIe and AXIGood reasoning and communication skillsMust have strong knowledge in PCIe Gen1/3/4/5 (Logical PHY, LTSSM, DLL & TL)Must have hands-…
Design Verification Engineer
Ambit Semiconductors
Hyderabad, Telangana
Understanding BIST would be an added advantage. Experience in the verification of IP cores. Must have proven experience in developing HVL (System Verilog/UVM)…
Lead Principal Engineer, Design Verification
Micron
Hyderabad, Telangana
8 to 16 years of experience in complex IC verification and/or IC design preferred. Solid knowledge of CMOS circuit design fundamentals and timing behavior.
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* Please note that all salary figures are approximations based upon third party submissions to SimplyHired or its affiliates. These figures are given to SimplyHired users for the purpose of generalised comparison only. Minimum wage may differ by region and you should consult the employer for actual salary figures.