Up Senior machine learning engineer Jobs – 71 Open Jobs Today

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Synopsys —Noida, Uttar Pradesh
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Websenor —Noida, Uttar Pradesh
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ASIC Digital Design, Sr Manager

Synopsys -
Noida, Uttar Pradesh

Apply Now

Job details

Benefits

Health insurance

Qualifications

English
Bash (Unix shell)
Verilog
Perl
Scripting
SystemVerilog
Communication skills
Python

Full job description

Senior Verification Manager - IP Development

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineering leader with a passion for driving excellence in ASIC verification. With more than 15 years of hands-on experience, you thrive in dynamic environments and possess a deep understanding of high-speed protocol design and verification. You value collaboration, mentoring, and empowering teams to achieve outstanding results. Your approach blends technical rigor with empathy and inclusivity, fostering a culture where every team member feels valued and motivated to contribute their best. You are adept at navigating complex challenges, balancing multiple projects, and adapting to evolving technologies. Communication is one of your strengths—you articulate ideas clearly, listen actively, and build consensus among stakeholders across functions. You are proactive, innovative, and always eager to learn, whether it’s exploring new verification methodologies or refining team practices for greater efficiency. Your leadership style is built on trust, transparency, and a commitment to continuous improvement, making you a catalyst for both technical advancement and team growth. You take pride in delivering fully verified, high-quality designs and supporting customers with diligence and professionalism. Above all, you are excited by the opportunity to make a tangible impact at Synopsys, shaping the future of silicon technology through your expertise and vision.

What You’ll Be Doing:

Lead and mentor a team of design and verification engineers, ensuring high performance and professional growth.
Own the verification strategy, environment architecture, and detailed verification plans for multiple complex ASIC projects.
Drive technical excellence by evaluating and implementing advanced development flows, including Verilog/SystemVerilog, test planning, behavioral modeling, and coverage analysis.
Collaborate closely with architects, designers, and VIP teams to deliver robust, functionally correct designs.
Identify design issues, propose corrective actions, and resolve inconsistencies in documented functionality.
Champion best practices in verification, continuously improving methodologies and execution efficiency.
Support customer issues through in-depth reproduction and analysis, delivering timely resolutions.
Balance multiple priorities and projects, adapting to new challenges and requirements as they arise.

The Impact You Will Have:

Ensure the functional correctness and completeness of high-performance silicon designs delivered to market.
Elevate team capabilities through mentorship, fostering a culture of learning and technical excellence.
Drive innovation in verification methodologies, enhancing product reliability and reducing time-to-market.
Facilitate seamless cross-functional collaboration, bringing together diverse expertise for superior outcomes.
Strengthen Synopsys’ reputation as a leader in ASIC verification and IP integration.
Deliver fully verified designs that empower customers and partners to build groundbreaking products.
Shape the strategic direction of verification practices, influencing industry standards and best practices.

What You’ll Need:

Extensive experience (15+ years) in ASIC design and verification, with a focus on high-speed protocols.
Strong proficiency in Verilog, VHDL, and/or SystemVerilog for hardware design and verification.
Hands-on knowledge of verification methodologies such as UVM, including environment architecture and coverage analysis.
Experience with scripting languages (BASH, TCSH, PERL, PYTHON, TCL) for automation and workflow optimization.
Proven ability to manage and lead high-performing engineering teams in fast-paced environments.
Exceptional problem-solving skills and attention to detail.

Who You Are:

An inclusive leader who values diverse perspectives and fosters a collaborative team environment
Effective communicator, skilled in both written and verbal English
Proactive and adaptable, comfortable with multitasking and shifting priorities.
Mentor and coach, dedicated to developing junior engineers and sharing expertise
Driven by curiosity and a desire to learn new technologies and methodologies.
Organized, reliable, and committed to delivering the highest quality results.

The Team You’ll Be A Part Of:

You will join a forward-thinking engineering team at Synopsys in Noida, dedicated to advancing ASIC verification for next-generation silicon solutions. The team is composed of talented engineers and technical leaders who work collaboratively across design, architecture, and verification functions. Our focus is on delivering fully verified, high-performance designs that set new industry benchmarks. You’ll play an integral role in shaping team culture, driving technical innovation, and supporting customer success worldwide.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Apply Now

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