Uttar Pradesh Hardware engineers Jobs – 101 Open Jobs Today

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SMTS-Verification IP
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Before our software developers write even a single line of code, they have to understand what drives our customers.
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Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5…

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Lead Engineer (IP Design & Microarchitecture)

Siemens -
Noida, Uttar Pradesh

Apply Now

Job details

Permanent | Full-time
11 hours ago

Qualifications

Public Relations
Doctoral degree
Signal processing
Master's degree
Bash (Unix shell)
Verilog
C++
C
Bachelor's degree
Public relations
SystemVerilog
Python

Full job description

Siemens EDA is a global technology leader in Electronic Design Automation (EDA) software. Our innovative tools empower companies worldwide to develop highly advanced electronic products faster and more cost-effectively. We're pushing the boundaries of technology and physics, enabling our customers to deliver superior products in the increasingly complex world of chip, board, and system design.

As a Hardware Accelerator Designer, you'll be at the forefront of this innovation, collaborating with algorithm architects and a talented team of designers. You'll play a crucial role in deriving architecture and micro-architecture decisions, and implementing and optimizing algorithms to transform them into low-power custom hardware accelerators using high-level synthesis methodologies.

What you'll do:
Develop, test, maintain, and improve design IPs for optimal Power, Performance, and Area (PPA).

Implement functionality in SystemC/C++ and ensure designs meet stringent Latency, Throughput, Area, and Power goals.

Perform comprehensive power, area, and performance trade-off analyses to identify the most efficient solutions.

Leverage High-Level Synthesis (HLS) to rapidly iterate and evaluate a wide range of possible implementations, narrowing down to the best-suited version.

Drive coverage closure and meet all other sign-off criteria for IPs within a high-level design and verification environment.

Author detailed design documents that clearly articulate your architectural and implementation choices.

What you'll bring:
5-10 years of experience in RTL design (Verilog, SystemVerilog, digital microarchitecture).

A Bachelor's/Master’s degree pr PhD Scholars with 6 years of relevant experience are preferred.

Proven experience in breaking down complex digital signal processing algorithms into Micro/RTL architecture, while effectively managing cost and quality trade-offs.

Proficiency in coding with C/C++/Python/Bash.

Experience with High-Level Synthesis (HLS) for ASICs or FPGAs is a significant advantage.

Knowledge of basic processor architecture.

Experience with the full ASIC design cycle (from specification through bring-up) is preferred.

We are Siemens

A collection of over 377,000 minds building the future, one day at a time, in over 200 countries. We're dedicated to equality and welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!

We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare.

Transform the everyday!

Apply Now

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hardware engineers jobs in uttar pradesh

Lead Engineer (IP Design & Microarchitecture)

SMTS-Verification IP

Sr/Staff AE for Physical Implementation RTL-GDS

Sr Engineer, Physical Design

Sr Consultant

SMTS-Verification IP role

Associate III - VLSI

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