Date posted 08/05/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent over a decade designing analog circuits that have to move data at speeds most engineers never touch, and you know that the difference between a SERDES that works in simulation and one that works in silicon is a hundred small decisions about layout, process variation, and timing handoff. You are the kind of engineer who reads a SerDes standard and immediately starts sketching architectures that push beyond what the spec requires because you see where the bottleneck will be two years from now. You do not wait for someone to tell you the PLL is the problem. You run the jitter budget, trace it back to the oscillator, and propose three solutions before the next design review. You have taped out circuits in FinFET nodes where a few femtofarads of parasitic capacitance can kill your bandwidth, and you have learned to work with layout engineers who understand that your redline is not optional. Mentoring matters to you, not because it looks good on a review, but because you remember the senior engineer who taught you how to read an eye diagram and you want to be that person for someone else. At Synopsys, you will work on Multi-Gbps SERDES IP that goes into chips that power data centers, automotive networks, and AI accelerators.
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Review high-speed SerDes standards including PCIe, Ethernet, USB, and CXL, and translate them into transceiver architectures and detailed sub-block specifications for Multi-Gbps NRZ and PAM4 designs
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Architect and design analog and mixed-signal circuits including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and ADC/DAC blocks for advanced FinFET and gate-all-around process nodes
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Collaborate with digital design teams on analog and digital co-design, calibration loops, adaptation algorithms, and timing handoff to ensure seamless integration and optimal performance
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Work directly with layout engineers to guide physical implementation, minimize parasitics, manage device stress and process variation, and ensure robust post-silicon performance
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Present simulation results, design trade-offs, and architectural decisions in internal reviews, customer meetings, and industry panel discussions
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Document design features, simulation methodologies, test plans, and characterization results, and support post-silicon bring-up and debug with electrical analysis and design iteration proposals
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Analyze customer silicon data and field performance to identify improvement opportunities and drive post-silicon design updates for next-generation IP releases
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Define the architectural direction for Synopsys SERDES IP, influencing product roadmaps and enabling next-generation connectivity standards across automotive, data center, and AI markets
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Deliver power, performance, and area improvements that directly affect the competitiveness of Synopsys IP in advanced process nodes and high-speed communication applications
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Solve post-silicon challenges that unblock customer tape-outs and ensure successful deployment of Synopsys IP in high-volume production chips
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Mentor analog designers across the team, raising the technical bar for circuit design, simulation methodology, and design-for-reliability practices
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Strengthen Synopsys leadership in Multi-Gbps SERDES by contributing to industry standards bodies, customer engagements, and technical publications
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Enable faster time-to-market for customers by streamlining design and verification flows and reducing silicon respins through robust pre-silicon validation
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Shape the future of high-speed analog design at Synopsys by driving advances in adaptive equalization, low-power PLLs, and signal integrity for next-generation process technologies
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MTech or MS with 8+ years or BTech or BS with 10+ years of hands-on analog IC design experience in Electrical Engineering, Computer Engineering, or a related field
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Proven track record of CMOS tape-outs in FinFET technologies with demonstrable experience in Multi-Gbps high-speed designs using NRZ and PAM4 modulation
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Deep expertise in SERDES sub-circuit design including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and data converters
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Strong understanding of analog and digital co-design, calibration and adaptation algorithms, and timing handoff between analog and digital domains
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Proficiency with schematic entry, physical layout collaboration, design verification tools, and SPICE simulators such as Spectre or HSPICE
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Experience with scripting languages such as TCL, PERL, or MATLAB for post-processing simulation data and automating design tasks
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Solid grounding in system-level budgeting for jitter, amplitude, and noise, and familiarity with signal integrity challenges including packaging parasitics, crosstalk, and channel loss. Experience with ESD protection, custom digital design, and design-for-reliability considerations such as electromigration, IR drop, aging, and self-heating is a plus
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You can walk into a design review, look at a jitter waterfall plot, and pinpoint the architectural bottleneck in under five minutes without needing a slide deck
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You push back when a specification does not make sense or when a layout decision will compromise performance, and you do it with data and a proposed alternative
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You are the engineer others come to when a circuit is not behaving and simulation does not match silicon, because you know how to debug across domains and find the real root cause
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You write clear, thorough documentation because you know that six months from now, someone else will need to understand your design choices and you want them to succeed
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You stay current with emerging process technologies, circuit techniques, and industry standards because you know that what works in 7nm will not necessarily work in 3nm
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You value collaboration and knowledge-sharing, and you take the time to explain a complex trade-off to a junior engineer or a non-technical stakeholder without losing the nuance
You will join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and focused on developing cutting-edge SERDES IP for advanced process nodes. You will have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
