Dl Validation engineer Jobs – 104 Open Jobs Today

Senior Formal Verification Engineer
TechBiz Global GmbH —Delhi, Delhi
- Full-time
- Remote
- Doctoral degree
- B.Sc
- Master's degree
Quick apply
Lead, Data Scientist
Bain & Company Inc —Delhi, Delhi
- Full-time
- Azure
- Master's degree
- Databases
Staff AI Agentic Automation Engineer
Educational Testing Service (ETS) —Delhi, Delhi
- Full-time
- Computer Science
- Salesforce
- AWS
- Paid time off
Quick apply
3d
Civil Billing Engineer
Moobel Muse LLP —Delhi, Delhi
- ₹45,000 - ₹75,000 a month
- Full-time
- AutoCAD
- Civil engineering
- Microsoft Excel
Quick apply
1d
Product Manager – Digital Public Health Program
The Antara Foundation —Delhi
- Master's degree
- Project management
- Product management
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Server Assembly Engineer – Data Center
ViewPixel India —Dwarka, Delhi, Delhi
- ₹20,000 - ₹40,000 a month
- Full-time
- Assembly
- Electrical experience
- Bachelor's degree
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Channel SE - Identity Security
Palo Alto Networks —Delhi, Delhi
- Full-time
- Azure
- Sales
- AWS
1d
Lead, Product Management & Innovation
Bain & Company Inc —Delhi, Delhi
- Full-time
- Bachelor's degree
- Product management
- Software development
Network Security Lab Manager, India
AlgoSec —Delhi, Delhi
- Full-time
- Azure
- Laboratory experience
- AWS
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Domain Consultant - Identity Security
Palo Alto Networks —Delhi, Delhi
- Full-time
- Azure
- English
- Java
2d
Fleet Data Specialist M-F
Safran —Delhi, Delhi
- Full-time
- Microsoft Excel
- Engineering
- Microsoft Office
Performance Testing Engineer
E Hook Systems —West District, Delhi
- Java
- Analysis skills
- JavaScript
Site Supervisor
Wintersonne Design Studio —Badarpur, Delhi, Delhi
- ₹5,000 - ₹15,000 a month
- Full-time
- Civil engineering
- CAD
- Supervising experience
- Paid time off
- Paid sick time
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T&T | Cyber: D&R | Assistant Manager | SIEM | Delhi
Deloitte —Delhi
- Analytics
(Senior/Staff) C++ Software Engineer, Infotainment (Shanghai/Beijing Based)
Tesla —Delhi
- Computer science
- C++
Area Sales Director
Intuitive Surgical —Delhi, Delhi
- Up to 50% travel
- Sales
- Engineering
Associate Specialist - Presales
Ingram Micro —Delhi, Delhi
- Full-time
- Engineering
- Bachelor's degree
- Computer networking
Architect
IPS-Integrated Project Services —Naraina, Delhi, Delhi
- Full-time
- AutoCAD
- English
- Microsoft Office
3d
Principal Engineer / Architect - Electrical - BESS Business Unit
Kimbal —Delhi, Delhi
- System design
- Electrical experience
- Bachelor's degree
Quick apply

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Senior Formal Verification Engineer

TechBiz Global GmbH
Delhi, Delhi

Quick apply

Job details

Full-time

Qualifications

Doctoral degree
B.Sc
Master's degree
Bash (Unix shell)
Bachelor's degree
M.Sc
Computer Engineering
Scripting
SystemVerilog
Electrical Engineering
Python
Design patterns

Full job description

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Quick apply

Refine Your Search

validation engineer jobs in dl

Senior Formal Verification Engineer

Lead, Data Scientist

Staff AI Agentic Automation Engineer

Civil Billing Engineer

Product Manager – Digital Public Health Program

Server Assembly Engineer – Data Center

Channel SE - Identity Security

Lead, Product Management & Innovation

Network Security Lab Manager, India

Domain Consultant - Identity Security

Fleet Data Specialist M-F

Performance Testing Engineer

Site Supervisor

T&T | Cyber: D&R | Assistant Manager | SIEM | Delhi

(Senior/Staff) C++ Software Engineer, Infotainment (Shanghai/Beijing Based)

Area Sales Director

Associate Specialist - Presales

Architect

Principal Engineer / Architect - Electrical - BESS Business Unit

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