Date posted 08/19/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent a decade or more in the trenches of memory layout, and you know that the difference between a memory that ships in millions of devices and one that dies in characterization is often a decision about routing, spacing, or symmetry made months before tapeout. You are the engineer who catches those decisions early, the one circuit designers trust to tell them what will actually work in silicon versus what looks good in a schematic.
You have built SRAM bit-cells at 5nm, debugged LVS mismatches that stumped entire teams, and optimized array structures for both density and yield in ways that became the template for future projects. When a foundry changes a design rule three weeks before signoff, you do not panic. You assess the impact, propose solutions, and keep the project moving.
Leading comes naturally to you, not because you seek authority but because people know you will give them the real answer, the technical tradeoff, the path that actually works. You mentor by doing, by showing engineers how to think through a problem, not just how to fix it. At this point in your career, you are shaping not just layouts but methodologies, automation strategies, and the technical direction of entire product lines.
At Synopsys, you will work on memory IP that powers AI accelerators, automotive SoCs, and next-generation data centers. The problems are hard, the stakes are real, and the team expects you to lead.
-
Lead complete physical layout development for advanced memory IP including SRAM, ROM, eDRAM, and emerging memory types across nodes from 3nm to mature technologies
-
Drive layout architecture decisions at every level: bit-cell topology, array organization, peripheral circuits, power distribution, and full memory integration
-
Define and implement layout methodologies that improve area efficiency, performance, power consumption, and manufacturability while meeting aggressive yield targets
-
Resolve complex DRC, LVS, ERC, and EMIR issues in dense memory structures, ensuring first-pass silicon success and working directly with foundry teams when rules or models need clarification
-
Lead RC extraction, parasitic analysis, and signal integrity optimization efforts, collaborating with circuit designers to close timing, power, and reliability on critical paths
-
Develop layout automation, generators, validation flows, and productivity tools using scripting languages to accelerate execution and improve design quality
-
Mentor staff and senior layout engineers across multiple projects and sites, providing technical guidance, reviewing critical design decisions, and supporting career development
-
Shape memory IP strategies that directly influence product competitiveness in AI, HPC, automotive, mobile, and cloud markets where performance and power define success
-
Establish layout methodologies and best practices used across Synopsys memory product families and development sites, raising the bar for execution quality
-
Accelerate project schedules by driving automation, process improvements, and reusable design frameworks that reduce iteration cycles and manual effort
-
Reduce technical and schedule risk by identifying and mitigating critical layout challenges early, before they become tapeout blockers or silicon respins
-
Improve yield and manufacturability through layout techniques, design-for-manufacturing practices, and close collaboration with process technology teams
-
Strengthen organizational capability by mentoring engineers, building technical depth across the team, and creating a culture of technical excellence
-
Deliver memory IP that meets the most demanding customer requirements for density, speed, power, and reliability in production silicon
-
Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related technical discipline
-
Typically 10+ years of hands-on experience in custom physical layout design with deep expertise in advanced memory IP development
-
Demonstrated success delivering memory IP across multiple advanced technology nodes and tapeouts, including SRAM, ROM, or eDRAM in production silicon
-
Deep expertise in memory layout including bit-cell design, array structures, sense amplifiers, decoders, redundancy circuits, I/O, and peripheral blocks
-
Strong proficiency with layout tools such as Synopsys Custom Compiler, Cadence Virtuoso, or equivalent custom design platforms
-
Advanced understanding of foundry design rules, DRC/LVS closure methodologies, reliability requirements, EMIR validation, and memory-specific constraints
-
Experience developing layout automation, scripting solutions, or methodology improvements that enhance productivity and quality is highly valued
-
You solve the layout problems that others escalate, the ones involving conflicting constraints, ambiguous rules, or tradeoffs that require deep technical judgment
-
You can sit in a design review with circuit designers and foundry engineers, absorb conflicting requirements, and walk out with a layout strategy that actually works for everyone
-
You build trust across teams by being direct about what is possible, what is risky, and what needs to change, and you do it without creating unnecessary friction
-
You mentor by showing engineers how to think through a problem systematically, how to prioritize when everything feels critical, and how to build layouts that survive the full product lifecycle
-
You stay organized across multiple projects, shifting priorities, and cross-site collaboration without losing sight of what matters most: delivering silicon that works
-
You care about the details, the spacing that affects yield, the symmetry that affects matching, the routing that affects performance, because you know those details define whether the product succeeds The Team You'll Be Part Of
Your recruiter will
