Chennai, Tamil Nadu
Job Summary
Candidates with 8 to 14 years experience is mandatory
Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems.
Experience in Full chip RTL integration
Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc.
Experience in RTL Synthesis
Scripting experience
Experience integrating IP's like PCIe, DDR, Ethernet etc.
Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there.
Expected to handle minimum 2 projects simultaneously
Experience in handling and interacting with clients across different Geos.
Excellent communication skills are mandatory.
Key Responsibilities
1. Design And Architect Large-Scale Solutions Utilizing Design Validation Principles And Frameworks, Ensuring Scalability, Performance, And Security Throughout The Development Lifecycle.
2. Train And Mentor Team Members On Design Validation Methodologies And Technologies To Cultivate A Skilled Workforce And Mitigate Delivery Risks.
3. Continuously Evaluate And Integrate Emerging Technologies Into Design Validation Processes, Ensuring The Delivery Of High-Quality, Future-Proof Solutions That Meet Client Expectations And Industry Standards.
4. Leverage Extensive Domain Knowledge And Technical Expertise To Gather Client Requirements, Deliver Tailored Solutions, And Formulate A Technology Strategy That Aligns With Overarching Business Goals.
Skill Requirements
1. Expert Knowledge In Design Validation Processes And Frameworks
2. Proficiency In Architectural Design Patterns And Best Practices
3. Strong Understanding Of Scalability, Performance, And Security Principles
4. Excellent Communication And Mentoring Skills
Other Requirements
1. Recommended Certifications: Togaf 9 Certification, Certified Information Systems Security Professional (Cissp) (Optional But Valuable)
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