Date posted 04/12/2026
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You are a passionate and highly skilled engineer who thrives in a collaborative, fast-paced environment. With a deep understanding of analog design principles, you have honed your expertise in static timing analysis (STA) and timing characterization over 4-8 years in the semiconductor industry. You are driven by curiosity and a desire to solve complex challenges, always seeking innovative solutions to enhance performance and reliability. Your experience allows you to confidently debug circuit-level issues, leveraging your proficiency in transistor-level design simulation. You are comfortable working with advanced tools like SiliconSmart and NanoTime, and your strong scripting skills enable you to automate tasks and streamline processes efficiently. You believe in fostering a culture of accountability and ownership, leading by example and inspiring your teammates to deliver their best. Your communication skills—both written and verbal—are a key asset, enabling you to build strong relationships with internal development teams and contribute meaningfully to cross-functional projects. You hold a BTech or MTech in Electronics or Electrical Engineering, and you are committed to continuous learning and professional growth. Your adaptability, attention to detail, and problem-solving mindset make you an invaluable member of any engineering team, and you are eager to play a pivotal role in advancing Synopsys’ technology leadership.
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Driving DDR, HBM, and UCIE timing generation and validation in partnership with circuit design and layout teams.
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Performing static timing analysis (STA) and timing characterization, ensuring robust timing constraints and accurate correlation with design requirements.
Debugging and resolving timing violations at both circuit and system levels, - ing deep transistor-level simulation expertise.
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Utilizing SiliconSmart, NanoTime, and advanced scripting to automate timing analysis workflows and improve efficiency.
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Collaborating closely with internal development teams to communicate findings, propose solutions, and implement best practices.
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Providing technical leadership, mentoring junior engineers, and championing quality and accountability throughout project lifecycles.
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Enabling Synopsys to deliver high-performance, reliable IP solutions for industry-leading clients in semiconductor technology.
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Ensuring the integrity and robustness of timing generation across critical product lines such as DDR, HBM, and UCIE.
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Accelerating design cycles through automation and advanced analysis, supporting Synopsys’ reputation for efficiency and innovation.
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Reducing risk and improving silicon success rates by identifying and resolving complex timing issues early in the design process.
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Enhancing collaboration across engineering functions, contributing to a culture of excellence and
