Quadric delivers its GPNPU as soft IP — RTL and implementation collateral — enabling customers to integrate our processor into their own SoCs across a range of process nodes and foundries. You will drive PPA optimization across IP configurations, build the scalable reference flows customers use to evaluate and integrate our IP, and provide hands-on implementation support to customers working toward their tapeouts.
Responsibilities PPA Optimization & Analysis
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Drive PPA analysis and optimization for Quadric GPNPU soft IP across process nodes and hardware configurations — timing, area, leakage, and dynamic power
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Apply low-power techniques (clock gating, multi-Vt, operand isolation) and synthesis/P&R knobs to hit frequency and area targets
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Characterize the IP design space across configurations and build PPA models that support customer evaluations and pre-sales engagements
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Partner with RTL and architecture teams early to quantify tradeoffs and influence design decisions before they become costly to reverse
Reference Flow Development
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Build and maintain a scalable RTL-to-GDS reference flow for Quadric soft IP that customers can use to evaluate, integrate, and close PPA in their own SoC environment
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Ensure the flow is portable across supported process nodes with clear BKMs, SDC templates, floorplan scripts, and integration guidelines
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Develop TCL and Python automation — and leverage AI coding tools such as Claude — to accelerate flow development, reduce manual effort, and improve repeatability
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Qualify EDA tool updates and benchmark QoR impact before rolling into the reference flow
Customer Integration & Tapeout Support
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Act as the primary PD contact for customers integrating Quadric soft IP, guiding them from evaluation through their SoC tapeout
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Help customers adapt the reference flow to their process node, foundry PDK, and internal design environment
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Triage and resolve customer-reported implementation issues — timing, congestion, power, or flow failures — working with internal teams to deliver fixes or updated collateral
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Support FAE and business development with PPA feasibility studies for new customer engagements
Collaboration & Documentation
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Work with architecture, RTL, and software teams to ensure IP deliverables meet customer-facing PPA targets
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Document methodologies, BKMs, and optimization learnings; maintain process node bring-up guidelines to support IP portability
Requirements
Education & Experience
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BS/MS in Electrical Engineering, Computer Engineering, or related field
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4+ years of ASIC or processor IP physical design experience focused on PPA optimization and flow development across advanced nodes
Technical Skills
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Proficiency with industry-standard physical design tools from Synopsys or Cadence (synthesis, place-and-route, and timing analysis)
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Experience with advanced FinFET process nodes (16nm and below); multi-node experience preferred
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Strong TCL scripting and Python automation skills
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Solid understanding of synthesis and P&R levers for PPA — timing paths, cell selection, congestion, and power intent
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Hands-on experience with low-power design techniques and MCMM timing analysis
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Comfort using AI tools (e.g., Claude, Copilot) to accelerate script development, automate repetitive EDA tasks, and improve workflow productivity
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Understanding of DFT concepts (scan, ICG bypass) and their physical design implications
Nice to Have
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Experience delivering soft IP to external customers or supporting SoC integrators through tapeout
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Background in AI accelerator, NPU, or DSP processor IP implementation
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Exposure to metrics-driven QoR tracking and large-scale synthesis run management
