Job Title: FC (Fusion Compiler) Physical Design Lead Engineer
Location: Bangalore, Karnataka
Experience Required: 10+ Years
Openings: 1
Job Summary
We are seeking an experienced FC (Fusion Compiler) Physical Design Lead Engineer to drive full-chip implementation and signoff activities for complex SoC designs. The ideal candidate will lead physical design execution from RTL to GDSII and collaborate with cross-functional teams to ensure successful tape-out delivery.
Key Responsibilities
- Lead full-chip physical design implementation and closure.
- Drive RTL-to-GDSII execution and methodology.
- Own full-chip integration and hierarchy management.
- Collaborate with RTL, STA, DFT, Verification, and Design teams.
- Drive timing, power, area, and congestion optimization.
- Support tape-out activities and mentor junior engineers.
- Ensure high-quality design signoff and delivery.
Required Skills & Qualifications
- 10+ years of progressive experience in Physical Design.
- Strong expertise in full-chip and sub-hierarchy integration.
- Proven tape-out experience on large SoCs.
- Strong understanding of RTL-to-GDSII flow.
- Experience in multi-voltage and low-power methodologies.
- Hands-on expertise with Synopsys Fusion Compiler (FC).
- Experience with Cadence Innovus is preferred.
- Strong leadership, mentoring, and communication skills.
Preferred Experience
- Advanced-node SoC implementation experience.
- Full-chip timing closure and signoff expertise.
- Experience working in cross-functional semiconductor teams.
Location
Bangalore, Karnataka
Apply Now
Interested candidates can share their updated resume to:
Jai Arravinth - 7305843470
Pay: ₹1,500,000.00 - ₹3,000,000.00 per year
Benefits:
- Paid sick time
- Provident Fund
Work Location: In person
