Role description
Desired Skills and Experience:
- Engineers is expected to be very good in Basic Fundamentals of C-MOS technology
- Expected to have a very good understanding of the PD Flow fand able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred)
- Should have hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc.
- Hands-on experience in floor planning, placement optimizations, CTS and routing.
Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk)
- Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor
- ( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm
- Exposure in DMSA flow for ECO generation and implementation.
- Good knowledge of VLSI process and scripting in TCL, perl .
Skills
vlsi design,floor planning,placement optimization,physical verification,sta,cadence,synopsys,5nm
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
