Date posted 04/05/2026
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ASIC Verification Engineer, Sr Staff
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an enthusiastic and accomplished RTL design expert with a proven track record in leading complex ASIC digital subsystems from concept to silicon. Thriving on technical challenges, you find deep satisfaction in delivering first-time-right RTL and architecting robust, scalable subsystems. Your experience spans multiple successful tape-outs, and you have earned a reputation for technical excellence, reliability, and mentorship within cross-functional teams.
You are energized by collaborating with diverse groups - design, verification, DFT, and implementation - to bring ambitious projects to fruition. You are meticulous in your approach, always striving for the highest quality standards, and have a strong grasp of industry-standard protocols such as UCIe, Ethernet, UALink and AMBA. Your expertise extends to low power design techniques and DFT architecture, and you are adept at translating requirements into high quality micro-architecture document and functional specification.
As a leader, you inspire and guide your peers, leveraging your 8+ years of experience to drive innovation, efficiency, and reliability. You are committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions. If you are eager to shape the next generation of digital IP subsystems and make a lasting impact in the semiconductor industry, we want to hear from you.
What You Will Be Doing:
-
Leading the complete subsystem lifecycle - from requirements gathering and architecture definition to final release phases.
-
Crafting subsystem architectures and developing comprehensive functional specifications.
-
Defining and implementing micro-architectures, ensuring compliance with best RTL coding practices.
-
Driving RTL linting, CDC, RDC and ensuring bug-free first silicon delivery.
-
Collaborating closely with verification, DFT, and physical implementation teams to ensure seamless project execution.
-
Integrating and supporting standard protocols such as UCIe, Ethernet, UALink, and AMBA within subsystem designs.
- ing low power design methodologies and ensuring DFT requirements are met at the architectural level.
-
Mentoring junior engineers and participating in technical reviews to foster innovation and knowledge sharing.
Location: Bengaluru is preferred. Open to Noida, Hyderabad.
The Impact You Will Have:
-
Enable the delivery of state-of-the-art digital IP subsystems that power next-generation silicon solutions.
-
Drive first-time-right RTL, reducing verification cycles and accelerating time-to-market for Synopsys products.
-
Ensure robust integration of industry-standard protocols, bolstering product interoperability and performance.
-
Elevate subsystem quality and reliability through rigorous design and quality assurance practices.
-
Foster a collaborative and innovative team culture, mentoring and inspiring colleagues to achieve their best.
-
Contribute to Synopsys’ leadership in the semiconductor industry by delivering high-impact, scalable IP solutions.
-
Shape architectural decisions that influence the future direction of digital IP design at Synopsys.
-
Enable the successful verification and deployment of high-performance Subsystem in leading-edge SoCs worldwide.
-
Drive quality that powers AI, automotive, cloud, and mobile applications at massive scale.
What You Will Need:
-
Minimum 8 years of direct experience in RTL design and subsystem architecture for complex ASIC/SoC projects.
-
Proficiency with standard protocols including UCIe, Ethernet, UALink, and AMBA.
-
Demonstrated expertise in low power design methodologies and DFT architecture.
-
Strong experience with RTL coding (Verilog/SystemVerilog), linting, CDC, RDC, and formal verification tools.
-
Proven ability to lead cross-functional teams through all project phases, from specification to silicon.
-
Solid understanding of the ASIC design flow, including synthesis, timing analysis, and physical implementation.
-
Experience with interface protocols and IP design/verification processes; knowledge of UCIe/Ethernet/UALink is highly desirable.
Who You Are:
-
Innovative thinker with a growth mindset, always seeking to learn and improve.
-
Exceptional communicator - able to clearly articulate ideas, issues, and solutions across diverse teams, able to bridge technical and non-technical stakeholders.
-
Collaborative leader who thrives in a multicultural, inclusive environment.
-
Mentor and role model for junior team members, fostering a culture of continuous improvement.
-
Analytical and meticulous, with strong problem-solving and debugging skills.
-
Initiative-taking and driven to deliver high-quality results in a demanding environment.
-
Initiative-taking and proactive, with a passion for continuous learning and professional development.
-
Adaptable and resilient in the face of complex challenges and changing priorities.
The Team You Will Be A Part Of:
You will join the Synopsys Digital IP Subsystem team, a dynamic group of engineers dedicated to pushing the boundaries of ASIC design. Our team is at the forefront of innovation, delivering high-performance, reliable, and scalable digital subsystems for global customers. We value diversity, collaboration, and technical excellence, working together to solve complex challenges and enable Synopsys’ leadership in the semiconductor industry.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an enthusiastic and accomplished RTL design expert with a proven track record in leading complex ASIC digital subsystems from concept to silicon. Thriving on technical challenges, you find deep satisfaction in delivering first-time-right RTL and architecting robust, scalable subsystems. Your experience spans multiple successful tape-outs, and you have earned a reputation for technical excellence, reliability, and mentorship within cross-functional teams.
You are energized by collaborating with diverse groups - design, verification, DFT, and implementation - to bring ambitious projects to fruition. You are meticulous in your approach, always striving for the highest quality standards, and have a strong grasp of industry-standard protocols such as UCIe, Ethernet, UALink and AMBA. Your expertise extends to low power design techniques and DFT architecture, and you are adept at translating requirements into high quality micro-architecture document and functional specification.
As a leader, you inspire and guide your peers, leveraging your 8+ years of experience to drive innovation, efficiency, and reliability. You are committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions. If you are eager to shape the next generation of digital IP subsystems and make a lasting impact in the semiconductor industry, we want to hear from you.
What You Will Be Doing:
-
Leading the complete subsystem lifecycle - from requirements gathering and architecture definition to final release phases.
-
Crafting subsystem architectures and developing comprehensive functional specifications.
-
Defining and implementing micro-architectures, ensuring compliance with best RTL coding practices.
-
Driving RTL linting, CDC, RDC and ensuring bug-free first silicon delivery.
-
Collaborating closely with verification, DFT, and physical implementation teams to ensure seamless project execution.
-
Integrating and supporting standard protocols such as UCIe, Ethernet, UALink, and AMBA within subsystem designs.
- ing low power design methodologies and ensuring DFT requirements are met at the architectural level.
-
Mentoring junior engineers and participating in technical reviews to foster innovation and knowledge sharing.
Location: Bengaluru is preferred. Open to Noida, Hyderabad.
The Impact You Will Have:
-
Enable the delivery of state-of-the-art digital IP subsystems that power next-generation silicon solutions.
-
Drive first-time-right RTL, reducing verification cycles and accelerating time-to-market for Synopsys products.
-
Ensure robust integration of industry-standard protocols, bolstering product interoperability and performance.
-
Elevate subsystem quality and reliability through rigorous design and quality assurance practices.
-
Foster a collaborative and innovative team culture, mentoring and inspiring colleagues to achieve their best.
-
Contribute to Synopsys’ leadership in the semiconductor industry by delivering high-impact, scalable IP solutions.
-
Shape architectural decisions that influence the future direction of digital IP design at Synopsys.
-
Enable the successful verification and deployment of high-performance Subsystem in leading-edge SoCs worldwide.
-
Drive quality that powers AI, automotive, cloud, and mobile applications at massive scale.
What You Will Need:
-
Minimum 8 years of direct experience in RTL design and subsystem architecture for complex ASIC/SoC projects.
-
Proficiency with standard protocols including UCIe, Ethernet, UALink, and AMBA.
-
Demonstrated expertise in low power design methodologies and DFT architecture.
-
Strong experience with RTL coding (Verilog/SystemVerilog), linting, CDC, RDC, and formal verification tools.
-
Proven ability to lead cross-functional teams through all project phases, from specification to silicon.
-
Solid understanding of the ASIC design flow, including synthesis, timing analysis, and physical implementation.
-
Experience with interface protocols and IP design/verification processes; knowledge of UCIe/Ethernet/UALink is highly desirable.
Who You Are:
-
Innovative thinker with a growth mindset, always seeking to learn and improve.
-
Exceptional communicator - able to clearly articulate ideas, issues, and solutions across diverse teams, able to bridge technical and non-technical stakeholders.
-
Collaborative leader who thrives in a multicultural, inclusive environment.
-
Mentor and role model for junior team members, fostering a culture of continuous improvement.
-
Analytical and meticulous, with strong problem-solving and debugging skills.
-
Initiative-taking and driven to deliver high-quality results in a demanding environment.
-
Initiative-taking and proactive, with a passion for continuous learning and professional development.
-
Adaptable and resilient in the face of complex challenges and changing priorities.
The Team You Will Be A Part Of:
You will join the Synopsys Digital IP Subsystem team, a dynamic group of engineers dedicated to pushing the boundaries of ASIC design. Our team is at the forefront of innovation, delivering high-performance, reliable, and scalable digital subsystems for global customers. We value diversity, collaboration, and technical excellence, working together to solve complex challenges and enable Synopsys’ leadership in the semiconductor industry.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
