- Execute end-to-end RTL to GDSII physical design flow for block, subsystem, and full-chip designs
- Perform floorplanning, power planning, placement, CTS, and routing
- Drive multi-corner multi-mode (MCMM) static timing analysis and closure
- Ensure physical verification signoff (DRC, LVS, ERC)
- Analyze and close IR drop, EM, and signal integrity issue
Desired Candidate Profile
Qualifications : BACHELOR OF ENGINEERING
