Role description
Looking for 5+years candidates with Minimum 1 year of hands-on experience in PCIe Gen5/Gen6
Job Description for 1 PCIe Req
- 5 to 8 years of experience in design verification in a fast-paced development environment.
- Strong understanding of the complete verification lifecycle, including test planning, testbench development, execution, debug, and coverage closure.
- Strong hands-on experience in SystemVerilog and UVM.
- Good working knowledge of PCIe and AMBA protocols.
- Minimum 1 year of hands-on experience in PCIe Gen5 or Gen6 is mandatory.
- Proven expertise in developing UVM testbench environments and verification components such as drivers, monitors, scoreboards, and agents from scratch.
- Self-motivated and result-oriented, with strong debugging, analytical, and communication skills.
Skills
vlsi design,pcie gen5,design verification,systemverilog,uvm,communication skills,analytical skills,uvm testbench,verification lifecycle,debugging
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
