Role description
- 6 to 10 years of experience in ASIC Design
- Strong Digital Design Knowledge
- RTL coding experience - System Verilog/Verilog/VHDL
- Working knowledge in CDC, Linting
- Experience in Synthesis/STA/DFT/Layout logs/reports review
- Knowledge in DDR preferable
- Debug skill of issues
Skills
vlsi design,asic design,system verilog,synthesis,rtl coding,digital design,cdc,linting,layout,sta
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
