Design verification of ASICs for Palladium.
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Position is based in Bangalore
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Will have to work at IP, Sub-System and SOC level verification.
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Test plan creation, functional coverage plan and coding of functional coverage bins.
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Will be involved in post silicon validation/bring up.
Job Requirements:
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Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology.
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Experience in functional coverage/code coverage/assertions development and closure.
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Experience in test plan creation.
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Exposure to PCIe and LPDDR verification.
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Strong debug skills
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Should be process oriented and have a passion for scripting/automation.
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Should be a good team player
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Effective cross-team communication and documentation skill is strongly preferred.
Minimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in related fields.
