Senior Engineer - Low Power Design

Ericsson -
Bengaluru, Karnataka

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Job details

18 hours ago

Qualifications

Buffer (application)
5G
R
Electronics Engineering
Master's degree
Bachelor's degree
ANSYS
M.Sc
Scripting
Agile
Python

Full job description

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About this Opportunity
Join Ericsson's cutting-edge journey to shape the future of 5G networks! As a Low-Power Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Low-Power Physical Design Engineer to own chip-level power estimation, analysis, and signoff using Synopsys PrimePower (PTPX) on high-performance, power-constrained SoC designs at advanced process nodes. You will define and drive power closure methodology, coordinate with RTL, physical design, and architecture teams to meet power budgets, and contribute to synthesis and STA flows as a secondary responsibility. This role is critical to the chip's power-performance story from early RTL through tape-out.

What you will do:

Dynamic Power Analysis

Own dynamic power analysis using Synopsys PrimePower (PTPX) across all design modes, workloads, and PVT corners.
Generate, annotate, and validate switching activity files (SAIF / VCD) from RTL and gate-level simulations for accurate power estimation.
Define representative workload scenarios and activity vectors for meaningful power measurement across use cases (active, idle, burst).
Perform clock-domain-level, block-level, and full-chip dynamic power breakdowns; identify high-power contributors and drive optimization.
Collaborate with RTL designers to implement low-power techniques — clock gating, operand isolation, fine-grained power gating — and verify their effectiveness in PTPX.

Static & Leakage Power Analysis

Perform leakage power analysis across process corners and temperatures; validate multi-Vt cell usage and leakage reduction strategies.
Analyze static power contribution from individual blocks and guide Vt optimization decisions in partnership with synthesis teams.
Validate UPF/CPF power intent implementation — isolation cells, level shifters, retention registers — for correctness and power impact.

Power Integrity & IR Drop

Coordinate with physical design and package teams on static and dynamic IR drop analysis using Ansys RedHawk or Synopsys VoltageStorm.
Analyze electromigration (EM) violations on power and signal nets; provide constraints and guidance to P&R for power grid fixes.
Define power delivery network (PDN) requirements and validate against IR drop targets throughout the design cycle.
Cross-correlate PTPX switching activity maps with IR drop hotspots to identify and resolve power integrity risks.

Power Signoff & Methodology

Define and own the power signoff checklist and sign-off criteria; lead power-related tape-out readiness reviews.
Build and maintain power estimation flows for early-stage RTL power budgeting and architecture trade-off studies.
Track power metrics across design milestones; produce detailed power reports for program management and architecture teams.
Develop and document power analysis methodology, scripts, and best practices for reuse across projects and technology nodes.
Engage with EDA vendors (Synopsys) to evaluate new PTPX features, resolve tool issues, and optimize flow runtime.

Synthesis Support

Assist synthesis team in reviewing QoR results from Design Compiler or Genus with a focus on power-aware optimization — multi-Vt assignment, clock gating inference, and operand isolation.
Provide power-driven feedback on synthesis constraints and strategies; validate that low-power RTL coding practices translate correctly through synthesis.
Review DFT-aware synthesis output to ensure scan and BIST insertion does not introduce unexpected switching activity or power overhead.

Static Timing Analysis Support

Contribute to STA reviews using PrimeTime — specifically for timing paths affected by power optimization changes (clock gating, Vt swaps, buffer insertion).
Validate that power-saving ECOs (gate sizing, Vt swaps) do not introduce timing regressions; flag and coordinate fixes with the STA team.
Support MMMC corner coverage for power-vs-timing trade-off analysis at critical operating points.

The skills you bring:

B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field with 10+ years in power analysis or low-power design roles
Expert-level PTPX / PrimePower proficiency
SAIF/VCD generation, annotation, and validation
Strong understanding of dynamic, static, and leakage power dissipation mechanisms
Experience with UPF/CPF multi-voltage design flows
Familiarity with IR drop tools (RedHawk, VoltageStorm)
Working knowledge of synthesis (Fusion Compiler)
Basic STA familiarity (PrimeTime)
Proficiency in Tcl; Python scripting a strong plus
At least one tape-out on 7nm or below

Nice to Have

Experience with architectural power modeling and early RTL estimation flows
Familiarity with P&R tools (Innovus, ICC2) for power-driven implementation
Knowledge of memory compiler power models and SRAM power characterization
Background in package-level power delivery and PDN co-design
Exposure to thermal analysis and junction temperature estimation
Familiarity with power-aware formal verification flows
Strong foundation in CMOS circuit theory, digital design, and power dissipation mechanisms (dynamic, short-circuit, leakage).
Analytical mindset with a track record of identifying and resolving complex power issues across large, multi-million gate designs.

EDA Tools & Environment
Synopsys PTPX / PrimePower, Ansys RedHawk, VC-LP, Synopsys VoltageStorm, VCS / Questa (SAIF/VCD), Fusion Compiler, Design Compiler, PrimeTime, Tcl / Python

.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”

Why join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: India (IN) || Bangalore

Req ID: 786040

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Grow with us

What you will do:

The skills you bring:

Nice to Have

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