DFX - DV Engineer
Location - Bangalore
Experience - 8 to 15yrs
Strong experience in SystemVerilog and UVM
Solid understanding of SoC/IP verification methodologies
Good debugging and problem-solving skills
Develop and execute verification plans using SystemVerilog/UVM
Perform functional verification of SoC/IP components
Debug failures across simulation, emulation, and silicon
Work closely with design and DFT teams for testability and coverage
Analyze and validate test patterns (ATPG/ATE)
Support post-silicon validation and bring-up
Pay: ₹1,000,000.00 - ₹2,500,000.00 per year
Work Location: In person
