Role description
JD: - Design Verification Engineer Role and Responsibilities: Independent Verification Ownership of IP DV. Collaborating with various cross functional teams at multiple geo locations as part of execution. Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts) Skill Requirements: 1. Must have experience in developing test benches for IP/Subsystems/SoC. 2. In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV. 3. Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities. 4. Strong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs. 5. Must h ave a strong domain expertise in one or more following areas - AXI/PCIe/UCIe. 6. Experience in Hybrid testbenches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.
Experience: 7 to 10 years
Skills
vlsi design,system verilog,soc verification,ip verification,systemc,subsystem verification
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
