Formal Verification
Location: Hyderabad
Job Description:
- Strong experience in Formal Verification methodologies
- Hands-on expertise in SystemVerilog Assertions (SVA)
- Solid understanding of RTL design and micro-architecture
- Experience with equivalence checking (LEC/SEC)
- Knowledge of CDC/RDC verification
- Good debugging skills using counterexamples and traces
Job Requirement:
- Jasper Gold experience, CC checks, Property checks and IOMUX verification
Experience (years) : 4-10 yrs
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
