As a Senior Physical Design Engineer, you will be responsible for executing the complete Physical Design flow from Netlist to GDSII, including floor planning, power planning, placement, clock tree synthesisers, routing and physical verification and sign off activities while achieving the best balance of power, performance and area(PPA). The candidate should be capable of analysing and resolving setup and hold timing violations, congestion issues, DRC/LVS errors, IR drop, electro migration (EM) and other physical design challenges. You will work closely with RTL, DFT,STA, Verification,Library and sign off teams to ensure seamless design integration, implement engineering change orders(ECOs), support tape-out activities and contribute to delivering high-quality silicon on schedule. Strong problem-solving skills, excellent debugging capabilities and experience working on advanced technology nodes are highly desirable.
Qualifications & Required skills:
- B.E/ B.tech/ M.E/M.tech in EEE,ECE, VLSI , electrical engineering or a related discipline.
- 5+ years of experience in semiconductor manufacturing
- Hands -on experience in end-to-end physical Design implementation from Netlist to GDSII
- Experience with advanced technology nodes
- Strong understanding of semiconductor design methodologies and physical Design concepts.
- proficiency in Cadence Innova and / or Synopsys ICC2
- Experience with Synopsis primeTime or cadence Tempus for STA
- Hands- on experience with calibre, starRC or other physical verification and extraction tools
- Experience in ECO implementation and Tape-out activities
Pay: ₹1,500,000.00 - ₹2,000,000.00 per year
Benefits:
- Paid sick time
- Paid time off
Work Location: In person
