Role description
We are looking for profiles with 6-8 years' experience in SoC RTL/DFx verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. It s good to have pattern generation and Silicon debug experience. Please let me know if you have suitable profiles.
Skills
vlsi design,verilog hdl,service operation center,system verilog,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
