Role description
Key Requirements: 4 6 years of SOC Design Verification (DV) experience with a strong focus on GPIO, sensos , CPU core verification, Debug Architecture, and eFuse verification.
Must possess solid knowledge of verification methodologies, testbench development, and coverage analysis for SOC projects.
Experience with SystemVerilog/UVM, scripting, and hardware debugging tools is essential.
Strong problem solving skills and the ability to work collaboratively in a cross functional team are required.
Skill Requirements: GPIO, Sensor ,Debug Architecture, and eFuse , SOC DV
Good to have: CPU core verification , Frequency Monitors
Experience: 4 6 years experience
Qualifications: B.Tech/B.E/M.Tech/M.E
Skills
vlsi design,gpio,soc design verification,systemverilog,scripting,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
