Job Title: CPUSS DV Engineer / Lead
Experience: 5–20 Years
Location: Bangalore / Hyderabad
Work Mode: Work From Office
Job Description
We are looking for an experienced CPUSS DV Engineer / Lead with strong expertise in CPU subsystem verification, SystemVerilog, UVM, cache verification, and RISC-V architecture. The candidate will be responsible for developing verification environments, debugging complex failures, and validating CPU/cache subsystem functionality.
Key Responsibilities
Develop and maintain SystemVerilog/UVM-based testbench environments for CPU and cache subsystems.
Perform functional verification of CPU pipeline units including Fetch, Decode, Schedule, Execute, and Load/Store Units.
Work on cache verification, including memory consistency, cache coherence, CHI protocol, coherence manager, and shared L1/L2/L3 cache.
Develop, debug, and execute assembly-level tests for CPU and subsystem verification.
Verify CPU features based on RISC-V architecture, preferably RVA23 standards.
Validate vector datapath operations for functional correctness and performance.
Debug failures across RTL, testbench, simulations, and verification environments.
Collaborate with design, architecture, and cross-functional teams to resolve issues and improve verification coverage.
Work Location: In person
