Lead the architecture, design, and verification of digital blocks for mixed-signal ASICs
Collaborate closely with Analog and System teams to define specifications and ensure seamless integration
Drive RTL design using Verilog/SystemVerilog and optimize for power, performance, and area
Follow the digital design flow from concept to tape-out, including synthesis, static timing analysis etc..
Guide and mentor digital designers and verification engineers
Interface with backend teams for physical design and support post-silicon validation
Contribute to IP reuse strategy and design methodology improvements
Participate in design reviews and provide technical leadership across cross-functional teams
