We are seeking a highly skilled and motivated Physical Design Engineer to join our dynamic team. The successful candidate will be responsible for the complete physical implementation of complex digital integrated circuits from RTL netlist to GDSII. This role involves working on advanced technology nodes and collaborating closely with front-end design, DFT, and verification teams to ensure timely and high-quality silicon delivery.
- Perform full-chip and block-level physical design activities including floor planning, power grid design, and block integration.
- Execute place and route (P&R) for complex digital designs, ensuring optimal area, power, and performance.
- Implement and optimize clock distribution networks using advanced Clock Tree Synthesis (CTS) techniques to meet ent timing requirements.
- Conduct comprehensive Static Timing Analysis (STA) and timing closure activities across all operating corners and modes.
- Perform physical verification (DRC, LVS, Antenna, ERC) and resolve any violations to achieve tape-out readiness.
- Analyze and optimize power consumption, including leakage and dynamic power, utilizing low power design techniques.
- Collaborate with front-end design engineers to understand design intent and resolve physical design-related issues.
- Develop and maintain scripts (TCL, Python, Perl) for design flow automation, efficiency improvements, and design analysis.
- Debug and resolve complex physical design issues related to timing, power, noise, and manufacturability.
- Work with cross-functional teams to ensure seamless integration and successful tape-out of silicon products.
- Stay updated with the latest industry trends, tools, and methodologies in physical design.
