Role description
JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.EXPERIENCE AND EDUCATION: 2-3 years of proven verification experience on large ASIC development projects experience in a hardware development setting;Strong background in SV/UVM, C, Regression management, SPI, I2C, UART, Ethernet, PCIe Protocol Knowledge, ARM Processor architecture knowledge in a Linux Environment;Strong debug skills and experience with debug tools such as VCS, Verdi;Proficient in Makefiles;Experience in Verilog/SystemVerilog/SystemC, preferred;Strong analytical skills and attention to detail;Excellent written and communication skills
Skills
vlsi design,regression management,asic,functional verification,ip cores,sv/uvm,spi,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.