We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
*
You Are*
You are a hands-on DFT expert who has driven test architecture and implementation for complex SoCs that tape out and succeed in production-not just in reviews. You understand how decisions made around RTL freeze impact coverage, yield, and test cost at volume, and you can confidently define the right strategy across scan/ATPG, MBIST/LBIST, and broader test hooks needed for bring-up and failure analysis.
You don’t just run tools-you understand the engineering tradeoffs between test time, area/power overhead, and coverage, and you can explain (and defend) why a specific approach is right for a given subsystem and product context. As a Principal Engineer, you operate with high autonomy, own technically complex deliverables end-to-end, and influence outcomes through deep expertise and strong cross-functional collaboration.
*
What You’ll Be Doing*
- Own DFT architecture, implementation, integration, and verification for complex SoCs/subsystems from specification through tapeout, working directly with customer and internal design teams
- Define and execute test strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations to meet coverage, quality, yield, and cost targets
- Drive DFT signoff readiness by identifying testability risks early, proposing design changes, and ensuring closure across the RTL-to-GDS flow
- Develop and institutionalize reusable DFT methodologies, checklists, and guidelines using Synopsys EDA tools to solve real customer problems on active service projects
- Partner with silicon validation and test engineering teams on post-silicon debug, failure analysis triage, and pattern refinement to improve production outcomes
- Collaborate closely with RTL design, functional verification, physical design, timing, and power teams to ensure testability is designed-in from architecture through signoff
- Provide technical guidance to peers through design reviews, integration/debug support, and best-practice sharing (without formal people management)
*
The Impact You Will Have*
- Enable first-pass silicon success by surfacing and resolving DFT issues before tapeout
- Improve test coverage and yield through robust scan/ATPG and BIST strategies aligned to product constraints
- Reduce production test time and cost for SoCs in high-performance computing, automotive, and aerospace domains
- Create reusable DFT methodologies that scale across multiple programs and customer engagements
- Strengthen customer confidence by delivering DFT solutions that work in production, not just in simulation
- Influence Synopsys tools/IP direction by feeding back real project learnings and customer pain points
*
What You’ll Need*
- Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, or related field
- Typically 10+ years of hands-on SoC DFT experience with proven depth in scan/ATPG, memory BIST, logic BIST, and analog test considerations
- Strong understanding of the end-to-end SoC design flow: microarchitecture → RTL → verification → synthesis → timing/physical implementation → signoff
- Demonstrated experience owning DFT implementation for complex SoCs that have taped out and gone to production
- Strong working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and/or BIST Architect (plus)
- Proven ability to work cross-functionally to resolve testability issues and drive closure under schedule constraints
- Post-silicon debug experience and collaboration with test engineering teams to refine production test programs (plus)
*
Who You Are*
- You can quickly identify untestable logic or weak test hooks and propose practical fixes that teams will adopt
- You are comfortable leading technical discussions with architects and pushing back when decisions introduce coverage gaps or yield risk
- You operate with high ownership and ambiguity tolerance-able to define a path forward with incomplete information
- You share expertise through hands-on collaboration, reviews, and problem-solving-not through org authority
- You communicate clearly, translating DFT tradeoffs into schedule/cost/yield impact for stakeholders
- You stay current with evolving DFT techniques because each new tapeout brings different constraints
*
The Team You’ll Be Part Of*
You will join the Systems Solutions Group (SSG), a team that delivers tool, methodology, architecture, design creation, design verification, and physical implementation expertise to help leading-edge customers complete their most challenging SoC design projects. The work spans from sub-blocks to full turnkey end-to-end SoCs for customers ranging from startups to industry leaders, commercial companies, and government agencies developing SoCs for high-performance computing, automotive, aerospace and defense, and more. This is a customer-facing role where the DFT solutions you build directly enable customer tapeouts and production success.
*
Rewards and Benefits*
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
