Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years turning gate-level netlists into actual silicon that works, and you know that the difference between a block that tapes out clean and one that comes back with a respin is usually a floor plan decision made in week two. You think in terms of power domains, clock trees, and routing congestion before anyone asks you to, because you have debugged enough DRC violations at 2 a.m. to know what breaks and why.
You are the engineer who can look at a block, see the macro placement problem before it becomes a timing problem, and fix it without waiting for someone to tell you it is broken. You have owned gate-to-GDSII flows end to end, not just run scripts but actually understood what each step does and why it matters for signoff.
You do not need hand-holding on MCMM setup or UPF constraints. You write them, you own them, and you know when they are wrong because the results tell you. When STA comes back with a violation or layout flags an antenna issue, you are the one who digs in, finds the root cause, and closes it.
At Synopsys, you will work on real ASIC blocks that ship in products, with access to the toolset that defines the industry and a team that expects you to know your craft.
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Implement digital blocks from gate-level netlist through GDSII using full ASIC physical design flow including design initialization, power planning, floor planning, macro placement, scan-chain reordering, clock tree synthesis, routing, and chip finishing
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Perform signoff verifications including DRC, LVS, and antenna checks for layout, and EMIR and ESD analysis for reliability on implemented blocks
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Write and own MCMM (multi-corner multi-mode) and UPF (Unified Power Format) constraint files for block-level designs
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Provide clean handoff data to STA, Formality, and layout and reliability verification teams to enable signoff closure
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Debug and resolve physical design issues related to timing, power, signal integrity, and manufacturability across advanced FinFET process nodes
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Collaborate with front-end design, verification, and signoff teams to ensure block-level implementation meets performance, power, and area targets
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Drive design closure on complex blocks, balancing trade-offs between timing, congestion, power, and physical constraints
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Enable successful tape-outs of ASIC blocks that power Synopsys IP and EDA products used across the semiconductor industry
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Reduce design iteration cycles by delivering clean physical implementations that pass signoff verifications on the first pass
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Improve design quality and robustness by catching and resolving floor plan, power, and routing issues early in the implementation flow
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Accelerate time-to-market for Synopsys products by providing reliable handoff data that enables faster STA and verification closure
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Contribute to the development and refinement of ASIC design methodologies and flows used across multiple product teams
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Mentor and guide junior engineers on physical design best practices, signoff requirements, and debugging techniques
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Help shape the technical direction of ASIC implementation strategies for next-generation FinFET and advanced node designs
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Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or equivalent field
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5+ years of hands-on experience in ASIC physical design, specifically gate-to-GDSII implementation flows
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Deep understanding of physical design stages including floor planning, power planning, placement, CTS, routing, and signoff verification
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Proficiency in writing and debugging MCMM and UPF files for multi-mode, multi-corner, and low-power designs
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Strong knowledge of layout verification (DRC, LVS, antenna) and reliability verification (EMIR, ESD) requirements and closure
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Experience with Synopsys toolset including Fusion Compiler or ICC2, PrimeTime, Formality, and ICV is highly desirable
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Exposure to FinFET process nodes and associated design challenges is a strong plus
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You can look at a floor plan and immediately spot the macro placement that will cause routing congestion three steps later
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You do not wait for signoff to tell you there is a problem, you run your own checks, catch issues early, and fix them before they escalate
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You can explain a complex trade-off between timing closure and power optimization to a design lead in two sentences without losing the technical nuance
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You are comfortable owning a block from netlist to GDSII, including all the messy middle steps where things do not go as planned
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You know when to push back on a constraint that does not make sense and when to work within it, and you can articulate the difference
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You treat handoff data like a contract, you make sure what you deliver to STA, Formality, and layout teams is complete, correct, and usable
Your recruiter will share more about the team structure and mission during the interview process.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
