Job Summary
We are looking for experienced ASIC/SoC Design Verification Engineers with strong expertise in SystemVerilog, UVM, and functional verification methodologies. The ideal candidate will be responsible for verifying complex digital designs, developing reusable verification environments, and ensuring first-pass silicon success.
Key Responsibilities
- Develop and execute verification plans, test cases, and verification strategies.
- Build and maintain reusable UVM/SystemVerilog based verification environments.
- Develop assertions (SVA), checkers, scoreboards, and functional coverage models.
- Perform block-level and SoC-level verification activities.
- Debug simulation failures and identify root causes efficiently.
- Execute regression testing and drive coverage closure.
- Verify industry-standard protocols such as AXI, AHB, APB, PCIe, USB, I2C, SPI, and UART.
- Collaborate closely with RTL, Architecture, DFT, and Physical Design teams.
- Participate in design reviews and support project sign-off activities.
Required Skills
- Strong hands-on experience in SystemVerilog and UVM.
- Good understanding of digital design fundamentals.
- Experience with assertions (SVA), functional coverage, and constrained random verification.
- Strong debugging and problem-solving skills.
- Knowledge of verification tools such as VCS, Xcelium, QuestaSim, or equivalent.
- Experience with scripting languages such as Python, Perl, TCL, or Shell scripting.
Pay: ₹1,000,000.00 - ₹3,000,000.00 per year
Benefits:
- Flexible schedule
- Health insurance
- Paid sick time
- Paid time off
- Provident Fund
Work Location: In person
