Role : Perform Synthesis for SOC and Blocks. Understand and develop synthesis/STA constraints.Perform timing Sign-Off and generate timing ECOs.
Desired Skills
- Good understanding of Synthesis/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF)
- Perform synthesis based on Power/Performance/Area/Schedule targets.
- Timing Constraints generation for synthesis and Timing signoff.
- Logical Equivalence between RTL to Netlist and Netlist to Netlist.
- Netlist handoff lint checks.
- Understanding of Timing closure with Analog PHYs and external interfaces like RGMII, GMII, SDHC, SPI etc. is a plus.
- Hands-on experience with Design compiler/RTL compiler/ Genus and primetime/tempus.
- Good scripting skills (TCL/Perl)
- Familiarity with PD concepts/flow and assist PD team if and when required
Experience : 2 to 3 Years
