No. of Positions : 2
Experience : 3-5 Years
Location : Bangalore
Key Skills / Highlights : High-Speed IOs such as MIPI MPHY UFS Gear 5/4/3, PCIe Gen4/3, USB4/USB3 Gen2/Gen1, HDMI, DP, DPoC etc. using hardware & software validation tools, oscilloscopes, BERT & logic analyzers.
Urgency : Immediate preferred
JD :
Key Responsibilities :
- Defining and executing the overall High-Speed IO IP Electrical test plans and validation strategy for AMD Semi-Custom SOC products including the compliance and logo testing related to the various High-Speed IOs such as MIPI MPHY UFS Gear 5/4/3, PCIe Gen4/3, USB4/USB3 Gen2/Gen1, HDMI, DP, DPoC etc. using hardware & software validation tools, oscilloscopes, BERT & logic analyzers.
- Working closely with supporting teams in SOC design, High-Speed IO IP development, Board Design, Simulation, firmware and diagnostics ensuring readiness for first silicon arrival, electrical characterization across PVT, submitting the test reports to different stake holders and blessing the IO.
- Participate and contribute to help in RCA of various High-Speed IO related issues throughout the development life cycle.
- Participate in enhancing AMD’s High-Speed IO validation capabilities, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
- Engaging with the various High-Speed IO suppliers in support of the SOC system development and the validation execution.
Preferred Experience:
- 5-12 years of IO Electrical and Logo Compliance Experience in at least one or several of Latest cutting Edge HSIOs such as UFS MIPI MPHY Gear 5/4/3, PCIe Gen6/5/4, USB4/3 etc.
- Working knowledge of any one or multiple High Speed IO technologies such as USB, HDMI, DP, DPoC, PCIe and others (SVI, I2C, JTAG etc.) that fall into a category we call MiscIO. Having a strong background in SI work with High-Speed IO technologies is a major plus.
- Solid understanding and vast experience on Test and characterization methodology of DDR or High-Speed IO interfaces which includes electrical compliance specifications such as eye diagram, differential signaling, jitter decomposition and analysis, Receiver-Jitter-Tolerance, transmission line considerations, Embedding/de-embedding, Measuring Various Types of channel losses, S-param measurements and Analysis, Phase Noise and Spectrum analysis, Spur measurements etc. through Latest HSIOs Lab Equipment.
- Experience in using High End oscilloscopes, J-BERT, Network analyzers ENA/VNA/TDR, spectrum analyzer, Phase Noise Analyzers, clock recovery, signal/function generators, Protocol, and logic analyzers etc.
- Good to have Team Lead capabilities with proven track record of technical expertise in the development & execution of platform level electrical & functional Compliance/Logo test plans.
- Should be able to use PCB design tools such as Orcad, Allegro, Mentor Graphics etc.
- Having working knowledge of any one of SI Simulation tools such as Ansys HFSS, Power-SI, Sigrity, ADS is a major plus.
- Hands on Experience and strong fundamentals on S-param Extraction, E2E channel Simulation, use of IBIS/AMI models, Simulation to Post Silicon measurements correlation for HSIOs can be a definite asset.
- Automation skills especially using Python or any other languages like C/C++, Perl, Ruby, C# is desirable.
- Must have excellent written and verbal communication skills for both internal and customer facing interaction.
- Attention to detail and the ability to analyze data quickly is a must.
