We are hiring Design verification Engineers PCIe Design IP R & D Team at Bangalore.
Skills: Strong Experience in SV/UVM/Test bench development, working knowledge of PCIe / CXL Protocol
Experience : 5+ yrs
Notice period: Immediate to 60 days
Salary : Best in Industry
Key Responsibilities:
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Lead end to end IP verification activities
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Develop detail test plans and verification strategies
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Build and maintain UVM based test benches using system verilog
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Knowledge of protocols (AXI/ AHB/APB) and PCIe is must
