Role : Perform verification using UVM and SVM on IP, Blocks and top.
Desired Skills:
- Ability to understand RTL quickly
- familiar with ASIC/FPGA verification methodology
- able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification
- should have the Knowledge of the System Verilog’s Universal Verification Methodology (UVM)
Experience : 2 to 3 Years
