Technical Lead / Principal DV Engineer – Test Automation Architecture
Department: Pre-Silicon Design Verification / Automation Engineering
Experience Level: 8 - 12 years
About the Role
We are seeking a highly skilled Principal Design Verification (DV) Engineer to pioneer the automated conversion of pre-silicon validation environments into post-silicon ATE test structures. In this role, you will serve as the foundational domain expert responsible for defining how complex, system-level "mission mode" test cases are structurally transformed into deterministic ATE test mode vectors.
You will not be responsible for building AI models or programming physical ATE testers. Instead, you will partner directly with our internal AI/LLM development team. Your deep expertise in UVM sequences, constrained-random stimulus, and SoC protocols will be the "brain" that guides the AI engine—specifying the translation rules, defining semantic guardrails, and auditing the generated outputs to ensure they are logically flawless for post-silicon deployment.
Key Responsibilities
1. DV-to-ATE Test Transformation Architecture
● Mission-to-Test Mode Mapping: Architect the methodology to translate dynamic, non-deterministic pre-silicon test suites (UVM sequences, virtual sequences, and directed C-tests) into structured, cycle-accurate test vectors suitable for ATE environments.
● Waveform & Event Extraction: Define the logic for extracting critical events, clocking relationships, and signal transitions from simulation files (VCD, FSDB) and mapping them to standardized test vector formats (such as STIL or WGL).
● Comprehensive Test Coverage Mapping: Categorize and prioritize all classes of DV tests (Functional, Power-Management, High-Speed IO initialization, and Security) into structured formats that automation tools can systematically parse.
2. AI Engineering Partnership & Domain Direction
● Ground-Truth Data Curation: Provide the AI/LLM engineering team with "golden" reference pairs (e.g., input UVM sequence vs. desired output vector format) to properly ground and train the models.
● Rule Engine & Guardrail Definition: Establish strict hardware boundaries (such as clock domain constraints, setup/hold windows, and reset sequences) that the AI tool must programmatically respect during translation.
● Output Quality Auditing: Review and audit the LLM-generated test structures for functional accuracy, ensuring the translated intent matches the original pre-silicon mission objective.
Required Skills & Qualifications
Technical Core: Advanced Design Verification
● Pre-Silicon DV Mastery: Expert-level knowledge of SystemVerilog and UVM (Universal Verification Methodology). Deep experience writing complex sequences, scoreboards, and virtual sequencers.
● Debug & Simulation Tools: High proficiency with industry-standard simulators (VCS, Questa, Xcelium) and debug environments (Verdi) to trace complex test executions.
● SoC & Protocol Expertise: Thorough understanding of SoC architectures, clock/reset structures, power states, and standard bus protocols (e.g., AMBA AXI, AHB, APB, PCIe).
● DFT/Test Mode Awareness: Strong conceptual understanding of how chips enter test modes (Scan, ATPG, JTAG, MBIST) and how mission-mode code interacts with these states.
Scripting & Automation
● Advanced capabilities in Python, Perl, or Tcl for parsing log files, manipulating text, and interfacing with EDA tool command-line interfaces.
Education & Experience
● Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
● Minimum of 8+ years of pure Design Verification experience.
● No prior experience with AI/LLM model creation or physical ATE hardware validation is required.
Preferred Qualifications
● Prior experience working on testbench migration, translating tests between different verification languages, or developing C-to-SV test framework bridges.
● A strong architectural mindset with a passion for removing the historical walls between pre-silicon verification and post-silicon testing team
Pay: ₹30,000.00 - ₹32,000.00 per month
Work Location: Hybrid remote in Bengaluru, Karnataka
