Role description
JOB DUTIES: Design and verify standard cell schematics. Port schematics into new technologies. Create new schematics for new functionality requirements. Verify circuit robustness using Monte Carlo simulation. Characterize standard cell libraries for custom PVTS. EXPERIENCE AND EDUATION: 0-2 years of relevant work experience; Experience with Schematic Design; Experience with Circuit Stimulation using Spice; Experience in Standard Cell Characterization using industry standard tools.
Experience - 3 to 7 years
Primary Skills
- Analog circuit design & spice simulations
Well-versed with industry standard EDA flows of Cadence/Mentor Graphics/Synopsys related to circuit design, EMIR & reliability
Strong in basics of R, L, C Network Theory, and CMOS Device fundamentals
Good to have:
Basic knowledge of analog layout
- Knowledge of scripting languages & automation tools (Perl, TCL, Skill, Ocean, python)
Debug and troubleshoot analog circuit issues
Skills
vlsi design,schematic design,analog circuit,circuit design,automation tools,industry standards,cadence,
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
