Job Description — ASIC / SoC Design Verification EngineerLocation
Remote / Hybrid / Onsite (Flexible)
Experience
4–10+ Years
Employment Type
Full-Time
About the Role
We are looking for an experienced ASIC / SoC Design Verification Engineer to develop scalable verification environments and comprehensive DV infrastructures for complex hardware IPs and SoC subsystems.
The ideal candidate should have strong SystemVerilog and UVM expertise along with hands-on experience verifying complex IPs and large-scale SoC environments. This role involves building reusable verification architectures, scalable regression systems, automated verification workflows, and advanced debug infrastructure for next-generation semiconductor and AI hardware platforms.
This is a high-impact engineering role suited for engineers who enjoy solving challenging verification problems, improving verification productivity, and working in fast-paced startup environments with strong ownership and autonomy.
Key Responsibilities
- Develop scalable UVM-based verification environments for ASIC and SoC subsystems
- Build reusable constrained-random verification architectures
- Create scoreboards, monitors, assertions, checkers, and protocol verification components
- Drive coverage-driven verification methodologies
- Develop and maintain regression, smoke, and sanity testing infrastructures
- Debug complex functional failures using waveform and protocol analysis
- Perform root-cause analysis for simulation and regression failures
- Collaborate closely with RTL, architecture, physical design, and validation teams
- Improve verification productivity through scripting and automation
- Contribute to CI-integrated verification workflows and scalable DV infrastructure
- Support advanced debug and verification closure activities
Required Skills
Strong expertise in:
- SystemVerilog
- UVM
- ASIC/SoC verification experience
- Experience verifying one or more of:
- LPDDR
- PCIe
- Ethernet
- NVLINK
- Processors
- NoCs
- Accelerators
- Protocol IPs
- Security IPs
- SoC subsystems
- Strong debugging and root-cause analysis capability
- Deep waveform analysis experience
- Assertion-based verification experience
- Coverage-driven verification expertise
- Experience with Synopsys and/or Cadence verification tools:
- VCS
- Verdi
- Xcelium
- SimVision
- DVE
Preferred / Nice-to-Have Skills
Experience with one or more of the following is highly desirable:
- Python, Bash, Perl, Tcl, or Makefile automation
- CI-integrated verification flows
- Automated regression orchestration
- AI-assisted verification workflows
- Waveform analysis automation
- LLM-assisted verification tooling
- Large-scale simulation farms
- Coverage closure automation
- Scalable verification infrastructure development
What We’re Looking For
- Strong ownership mindset
- High execution capability
- Independent problem-solving ability
- Strong debugging instincts
- Ability to work in fast-paced startup environments
- Excellent collaboration and communication skills
- Passion for building scalable verification systems and methodologies
Tools & Environment
The engineering team uses modern verification and AI-assisted engineering workflows, including:
- Synopsys verification ecosystem
- Cadence verification ecosystem
- CI-integrated regression systems
- AI-assisted engineering tooling
- Internal verification productivity infrastructure
Compensation may vary significantly based on:
- Protocol expertise
- CPU/GPU/AI accelerator verification experience
- SoC complexity handled
- UVM architecture ownership
- Advanced debug capability
- Verification automation expertise
- Startup execution ability
Pay: ₹658,590.48 - ₹1,000,815.06 per year
Work Location: In person
