Key responsibilities of the position are:
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Working with product engineers, customer support, and R&D to determine training requirements
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Creating and updating training lectures, labs, exams, and demos aligned with software and language standards releases and with high levels of quality
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Designing and developing lectures, labs, and demos that are deployed both online and in the classroom
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Delivering courses in a classroom or virtual setting
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Creating narrated online videos educating customers on how to use tools, languages, and methodologies
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Supporting online training customers when there are questions related to lectures and labs
A prospective candidate must have:
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A BSEE or MSEE degree
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Minimum 2 years of experience with SystemVerilog coding, UVM methodology projects, testbench creation, Simulation and Debug areas.
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Mandatory experience-exposure to low-power simulation and Functional safety simulation for at least 2 years
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Ability to author, analyze, and debug scripts in languages such as Bash, Perl, Python, and TCL
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Strong programming and HDL design and verification skills
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Ability to quickly analyze verification environments and design complexity
The selected candidate will:
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Excel at multitasking
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Expect to engage in a mixture of activities – authoring content, learning new tools and methodologies, “being the expert,” teaching and interacting with customers, and working with highly competent and experienced engineers.
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Given clear goals, work independently to accomplish such goals
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Have excellent written and verbal English communication skills
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Be well experienced using multimedia authoring tools, including Microsoft PowerPoint, Microsoft Word, and Adobe Acrobat and Photoshop (or equivalent), and audio/video tools such as Camtasia and Sound Forge.
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Be detail-oriented, well-organized, and receptive to challenges.
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Proactively react to resolve issues impeding progress
