Verification Engineer

Job details

SV-UVM based verification of SoCs, IPs and Subsystems
Building test environment using VIPs, coding missing components, testcases, checkers, coverage
Developing VIPs - architecture, code development and verification
Verification execution - debug, coverage analysis, regression management
Documentation - Verification strategies, planning, architecture, reports, handover documentation
Code management - Perforce or any other
Scripting with Perl, Python, Make files and unix-shells
C-based coding for testcases to be re-used in Emulation
In-depth understanding of protocols like 5G, DDR, PCIe, USB, SATA, HDMI, Video Codecs, NoC, UART, AMBA, I2C
Team work and communication within the company and across geographies
We High quality VLSI development work opportunity to architect and build testbenches,VIPs

3+ years of verification experience.
Subsystem and Chip level verification.
Verilog, System Verilog and UVM methodology.
PCIe, USB, LPDDR and Ethernet is plus.
Experience of verifying processors and Signal processing is plus.
Solid verification skills in problem-solving, constrained random testing, and debugging.

Excellent communication and interpersonal skills
Self motivated
Take ownership of problems
Creative problem solving
Strong and effective presentation skills, able to operate at multiple levels including senior management
Team player