Role: DFT Engineer
Location: Bangalore
Experience: 5 to 8+ Years
Notice Period: Immediate Joiners Preferred
Mandatory Skills:
· Strong experience in Design for Test (DFT) implementation
· Hands-on experience with Scan Insertion, Scan Compression, ATPG, MBIST, and LBIST
· Experience with Tessent, Synopsys DFT Compiler, TetraMAX, or Cadence Modus
· Strong understanding of DFT architecture and test methodologies
· Experience in Pattern Generation, Pattern Validation, and Coverage Analysis
· Knowledge of JTAG (IEEE 1149.1), Boundary Scan, and DFT Verification
· Experience with Gate-Level Simulation (GLS) and debugging
· Good understanding of Synthesis, STA, and RTL Design Flow
· Experience in SoC/IP-level DFT Integration and Silicon Bring-up is preferred
Pay: ₹2,000,000.00 - ₹2,700,000.00 per year
Work Location: In person
