Education: BE/ B Tech/ ME/ M Tech / MS : Expr 6 – 15 (T3/T4)
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B.Tech/BE/ME/Mtech with hands-on experience physical design , timing closure and physical verification.
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Exp with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
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Solid knowledge on physical design flow, Timing closure and physical verification. Knowledge of formal verification, EM-IR .
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Good track records of working on complex IP’s & SoC’s below 7 nm
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Power user of Cadence implementation tools, such as Genus, Innovus, Quantus,Tempus, PVS, Voltus.
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Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/Python.
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Any AI expr is add on.
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Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills.
