BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.
Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL required.
Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental exposure).
Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs.
Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning techniques.
Proven experience with formal verification and/or UVM-based verification methodologies, not limited to directed testbenches.
Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW boundary.
Version control experience using Git or similar tools.
Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world.
Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment.
Patents or published work in FPGA architecture, high-speed digital design, or DSP.
Experience defining test strategies for multi-Gbps compliance testing (particularly relevant for T&M product development).
General purpose microprocessor and DSP systems, PCIe, high-speed digital board design, PLL design, and analog signal conditioning experience.
Simulation experience using Siemens Questa, Aldec Riviera, or similar tools.
Contribution to or deep familiarity with open verification methodologies (e.g., cocotb, UVM community contributions).
Utilization of generative AI tools to assist in concept and implementation of FPGA designs.
