Key Responsibilities:
- Define, influence DFT architecture for subsystems and SoCs, achieving automotive-grade Safety and Security standards for logic and memory tests.
- Collaborate with IP teams, Systems, and Architecture teams to derive requirements, co-develop microarchitecture, and align DFT goals for IPs, subsystems, and SoCs.
- Work closely with Product and Test Engineering teams to understand test needs, provide DFT solutions, debug issues, and optimize test costs.
- Partner with cross-functional teams (RTL, DV, PD) to ensure high-quality and timely DFT implementation.
Qualifications and Skills:
Education: Bachelor’s or Master’s degree in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), Computer Science (CS), or a related field.
Experience: >4 years of hands-on experience in DFT aspects of SoC Design.
Technical Expertise:
- Strong understanding of Verilog/VHDL and DFT concepts for testability design.
- Proficient in implementation of Scan architectures including scan compression, memory test techniques, low pin count multi-site test methodologies.
- Experience with silicon bring-up and debugging.
- Familiarity with industry-standard tools like Modus, Genus, Xcelium, and Jasper.
- Good understanding of constraints, timing concepts, and test methodologies.
Soft Skills:
- Excellent problem-solving and debugging capabilities.
- Strong written and verbal communication skills for effective collaboration and reporting.
- Commitment to continuous learning and maintaining a high focus on quality.
- Ability to thrive in a team-oriented environment.
Preferred Qualifications:
- Experience with mixed-signal analog designs and DFT for Analog modules, generation of functional test patterns for Analog and Flash testing
- Familiarity with advanced automation scripting using Python, Perl, or TCL.
