Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CADbased automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and thirdparty vendor teams to continuously improve physical design methodologies and efficiencies.
Minimum Qualifications: • Bachelor's/master's degree in electrical / computer engineering, Computer Science, or in a STEM related field of study. • Experience in leading small team of engineers. • 14+ years of experience with complex ASIC/SOC Implementation. • Experience in system and processor architecture. • Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller. • Experience with System Verilog/SOC development environment. • Experience in scripting languages (i.e. PERL, TCL, or Python). • Experience with Hardware validation techniques (i.e., formal Verification, Test and Function Verification). • Preferred Qualifications: • Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study. • Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc) • Experience with interaction of computer hardware with software • Experience with Low power/UPF implementation/verification techniques. • Experience with Timing Analysis / Physical Verification / Formal verification techniques.
Experienced Hire
Shift 1 (India)
India, Bangalore
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
