Chennai, Tamil Nadu
Job Summary
SAP Deposits Management / Account Management (the TRBK core) configuration literacy — product master, condition types, interest and fee logic.
SAP FS-CML (Consumer & Mortgage Loans) and CMS (Collateral Management) — critical given the hard CML/CMS dependencies on the programme.
Business Partner (BP) master data and account lifecycle.
Payments, settlement (FI-CA contract accounts), and batch/end-of-day cycle behaviour.
Fioneer solution awareness (as functional partner) — where standard vs. bespoke config sits.
Analysis skills
Requirements elicitation, FSD/BRD authoring, and Requirements Traceability Matrix (RTM) discipline.
Legacy-vs-target gap analysis (BAS9 S/4HANA), as-is/to-be process mapping.
Interface/integration mapping and data-mapping validation.
SIT scenario design support, defect triage, and functional root-cause analysis.
Key Responsibilities
SAP Deposits Management / Account Management (the TRBK core) configuration literacy — product master, condition types, interest and fee logic.
SAP FS-CML (Consumer & Mortgage Loans) and CMS (Collateral Management) — critical given the hard CML/CMS dependencies on the programme.
Business Partner (BP) master data and account lifecycle.
Payments, settlement (FI-CA contract accounts), and batch/end-of-day cycle behaviour.
Fioneer solution awareness (as functional partner) — where standard vs. bespoke config sits.
Analysis skills
Requirements elicitation, FSD/BRD authoring, and Requirements Traceability Matrix (RTM) discipline.
Legacy-vs-target gap analysis (BAS9 S/4HANA), as-is/to-be process mapping.
Interface/integration mapping and data-mapping validation.
SIT scenario design support, defect triage, and functional root-cause analysis.
Skill Requirements
1. Expert proficiency in SoC architecture and design, with in-depth knowledge of Verilog and UVM for digital verification.
2. Excellent understanding of C and C++ development as applied to embedded systems and SoC integration.
3. Strong familiarity with RTL design, simulation tools (e.g., Synopsys VCS, Cadence), and advanced verification methodologies.
4. Advanced proficiency in developing and reviewing testbench architectures using UVM.
5. Solid experience in mentoring technical teams and driving best practices in SoC development.
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